1. Field of the Invention
The present invention relates to logic circuitry including a test point to detect a delay fault propagating on a logic path between input and output terminals, the test point being connected to the logic path, and also relates to a recording medium containing design data about the logic circuitry.
2. Description of the Related Art
In a process of manufacturing logic circuitry, a quality test is conventionally performed to provide high-quality products. For example, in a semiconductor integrated circuit including a plurality of logic circuits, a delay test to detect a delay fault is performed.
FIG. 1 illustrates an example of a configuration of conventional logic circuitry 900. FIG. 2 is a circuit diagram illustrating an example of a configuration of a logic circuit 901 in the logic circuitry 900. The logic circuitry 900 includes a plurality of circuits (logic circuits 901 to 903) having logic gates, which are placed between an input terminal (input FF: flip-flop) and an output terminal (output FF: flip-flip) The logic circuits 901 to 903 are mutually connected via a logic path 910 on which a signal propagates from the input terminal to the output terminal. A signal propagates on the logic path 910 from the input terminal through the logic circuits 901, 902, and 903 to the output terminal. As described above, each of the logic circuits (e.g., the logic circuit 901) in the logic circuitry 900 is constituted by a combination of logic gates, as illustrated in FIG. 2.
As a typical method for performing a delay test in the above-described logic circuitry 900, a method of inputting signals of predetermined patterns can be used. In this method, a delay fault occurred in the logic circuits 901 to 903 is detected by monitoring input of signal transition to the input terminal and output of signal propagation observed at the output terminal after propagation through the logic circuitry 900. At this time, setting of patterns of signals to be input to the input terminal is adjusted in accordance with whether a delay fault occurs in any of the circuits. That is, a test is performed by inputting signals each having a pattern allowing the signal about an occurred delay fault to propagate to the output terminal.
For example, when a delay fault occurs in the logic circuit 901, a signal about the delay fault is output from the logic circuit 901 to the logic path 910 (between the logic circuits 901 and 902). The output signal about the delay fault propagates to the logic circuits 902 and 903 in subsequent stages in order via the logic path 910 (between the logic circuits 901 and 902). The signal about the delay fault means a signal in a fault state that is delayed by predetermined time due to the fault occurred in the logic circuit 901 after being input to the input terminal.
In the delay test, setting is done so that the signal about the delay fault propagates to the output terminal. Specifically, the pattern of the signal to be input to the input terminal is designed so that the signal about the delay fault does not change in the logic circuit 902 when being input to the logic circuit 902 after propagating on the logic path 910 from the logic circuit 901 and that the signal passes through the logic circuit 902 while being kept in an original state. The signal about the delay fault passed through the logic circuit 902 further propagates on the logic path 910 (between the logic circuits 902 and 903) from the logic circuit 902 and is input to the logic circuit 903. In this logic circuit 903, too, the signal about the delay fault should not change and pass therethrough while being kept in the original state. Thus, the signal to be input to the input terminal needs to have a pattern for an effect of both the logic circuits 902 and 903. During execution of the delay test, signals of patterns designed in view of a delay fault that would occur in the respective logic circuits 901 to 903 are sequentially input.
In recent years, a method of connecting a test point to an arbitrary position of the logic path 910 of the logic circuitry 900 has been widely used. The test point is broadly classified into a controllability test point or an observability test point according to its function.
FIG. 3 is a circuit diagram illustrating a configuration in which a controllability test point 1100 connects to the logic circuit 901 illustrated in FIG. 2. The test point 1100 is capable of generating a signal about a delay fault in the logic circuit 901 in a pseudo manner and allowing the generated signal to propagate from the logic circuit 901 to the logic path 910 connected to the logic circuit 902 (see FIG. 1). That is, a delay test of the logic circuits 902 to 903 can be easily performed by controlling the test point 1100.
FIG. 4 is a circuit diagram illustrating a configuration in which an observability test point 1200 connects to the logic circuit 901 illustrated in FIG. 2. The test point 1200 detects a signal about a delay fault from the logic path 910 between the logic circuits 901 and 902 when the delay fault occurs in the logic circuit 901. If a logic circuit is provided in a previous stage of the logic circuit 901 and if such a pattern that a signal passes through the logic circuit 901 is input, a signal about a delay fault in the logic circuit in the previous stage can be detected.
However, in the above-described method for detecting a signal about a delay fault from the output terminal, the number of patterns of signals to be input to the input terminal at a test becomes enormous, if the configuration of the logic circuitry 900 is complicated and if the number of logic circuits increases. As a result, the amount of information processed at the test increases and the speed of generating the test decreases disadvantageously.
Detection of a delay fault is performed at every system cycle of the logic circuitry to be tested. In that case, if a delay fault occurred in the logic circuitry is slight relative to the system cycle in the method using the test point, as illustrated in FIGS. 3 and 4, it is possible that the test point does not function. For example, a signal about a delay fault detected by an observability test point in an intermediate stage of the logic circuitry 900, e.g., the logic path 910 connecting the logic circuits 901 to 903, is not detected as a delay fault. Also, even if signal transition is generated by a controllability test point, that is not detected as a fault at the output terminal. In this way, a slight delay fault cannot be detected in a delay test, which degrades the quality of the delay test.